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fractional-n rf/integer-n if dual pll s1m8836/37 1 introduction the s1m8836/37 is a fractional-n frequency synthesizer with integrated prescalers, designed for rf operation up to 1.0ghz /2.5ghz and for if operation up to 520mhz. the fractional-n synthesizer allows fast-locking, low phase noise phase-locked loops to be built easily, thus having rapid channel switching and reducing standby time for extended battery life. the s1m8836/37 based on s - d fractional-n techniques solves the fractional spur problems in other fractional-n synthesizers based on charge pump compensation. the synthesizer also has an additional feature that the pcs/cdma channel frequency in steps of 10khz can be accurately programmed. the s1m8836/37 contains quadruple-modulus prescalers. the s1m8836 rf synthesizer adopts an 8/9/12/13 prescaler(16/17/20/21 for the s1m8837) and the if synthesizer adopts an 8/9 prescaler. phase detector gain is user-programmable for maximum flexibility to address is-95 cdma and imt2000. various program-controlled power down options as well as low supply voltage help the design of wireless cell phones having minimum power consumption. using the samsung's proprietary digital phase-locked-loop technique, the s1m8836/37 has a linear phase detector characteristic and can be used for very stable, low noise pll's. supply voltage can range from 2.7v to 4.0v. the s1m8836/37 is available in a 24-qfn package. features high operating frequency dual synthesizer operating voltage range : 2.7 to 4.0v low current consumption(s1m8836: 5.5ma, s1m8837: 7.5ma) selectable power saving mode ( icc = 1ua typical @3v) quadruple-modulus prescaler and fractional-n/integer-n: ? s1m8836 (rf) 8/9/12/13 fractional-n ? s1m8837 (rf) 16/17/20/21 fractional-n ? s1m8836/37 (if) 8/9 intege r-n s1m8836: 250mhz to 1.0ghz (rf) / 45mhz to 520mhz(if) s1m8837: 500mhz to 2.5ghz(rf) / 45mhz to 520mhz(if) excellent in-band phase noise ( ? 85dbc/hz @ pcs, ? 90dbc/hz @ cdma) improved fractional spurious performance ( < 80dbc ) frequency resolution (= 10khz/64 @ f ref = 9.84mhz) fast channel switching time: <500us programmable charge pump output current: from 50 m a to 800 m a in 50 m a steps programmability via on-chip serial bus interface 24-qfn-3.5 4.5
s1m8836/37 fractional-n rf/integer-n if dual pll 2 applications high-rate data-service cellular telephones (for cdma) : s1m8836, s1m8837 high-rate data-service portable wireless communications : s1m8837 other wireless communications systems ordering information device package operating temperature + s1m8836x01-g0t0 24-qfn-3.5 4.5 -40 to +85c + s1m8837x01-g0t0 +: new product
fractional-n rf/integer-n if dual pll s1m8836/37 3 block diagram fold data out multiplexer rf ld if ld rf charge pump rf phase detector if charge pump if phase detector rf prescaler prescaler control + - rf programmable counter rf n-latch frac-n latch & s -d modulator rf r-latch rf reference counter if prescaler prescaler control if programmable counter if n-latch if r-latch if reference counter 20-bit shift register - + 2-bit control 1 2 3 4 5 6 7 8 9 21 20 19 18 17 16 15 14 13 10 11 12 24 23 22 out0 out1 v dd if v dd rf v p rf cp o rf dgnd f in rf gnd rf v dd rfa oscin f o ld rf_en if_en clock data le gnd if f in if f in if dgnd cp o if v p if f in rf
s1m8836/37 fractional-n rf/integer-n if dual pll 4 pin diagram 24-qfn 9 8 oscin v dd rfa 7 6 gnd rf f in rf 5 4 f in rf dgnd 3 2 cp o rf v p rf 1 v dd rf clcok data le gnd if f in if f in if dgnd cp o if v p if 10 fold rf_en if_en out0 out1 v dd if 11 12 24 23 22 13 14 15 16 17 18 19 20 21 s1m8836/37
fractional-n rf/integer-n if dual pll s1m8836/37 5 pin description pin no. symbol i/o descriptions 1 v dd rf ? rf pll power supply (2.7v to 4.0v). must be equal to v dd if. 2 vprf ? power supply for rf charge pump. must be 3 v dd rf and v dd if. 3 cporf o rf charge pump output. connected to an external loop filter. 4 dgnd ? ground for rf pll digital circuitry. 5 finrf i rf prescaler input. small signal input from the external vco. 6 finrf i rf prescaler complementary input. for a single-ended output rf vco, a bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. 7 gndrf ? ground for rf pll analog circuitry. 8 v dd rfa ? pll power supply (2.7v to 4.0v) for rf analog ( prescaler). must be equal to v dd rf 9 oscin i oscillator input to drive both the if and rf r counter inputs. 10 fold o multiplexed output of n or r divider and rf/if lock detect. 11 rf_en i rf pll enable (enable when high, power down when low). controls the rf pll to power down directly, not depending on a program control. also sets the charge pump output to be in tri-state when low. powers up when high depends on the state of rf_ctl_word. 12 if_en i if pll enable (enable when high, power-down when low). controls the if pll to power down directly. the same as rf_en except that power-up depends on the state of if_ctl_word. 13 clock i cmos clock input. data for the various counters is clocked into the 22-bit shift register on the rising edge. 14 data i binary serial data input. data entered msb (most significant bit) first. 15 le i load enable when le goes high. high impedance cmos input. 16 gndif ? ground for if analog circuitry. 17 f inif i if prescaler complementary input. for a single-ended output if vco, a bypass capacitor should be placed as close as possible to this pin. 18 finif i if prescaler input. small signal input from the vco. 19 dgnd ? ground for if pll digital circuitry. 20 cpoif o if charge pump output. connected to an external loop filter. 21 vpif ? power supply for if charge pump. must be 3 v dd rf and v dd if. 22 v dd if ? if pll power supply (2.7v to 4.0v). must be equal to v dd rf . 23 out1 o programmable cmos output. level of the output is controlled by w2[19] bit. 24 out0 o programmable cmos output. level of the output is controlled by w2[18] bit. in the speedy lock mode, the out0 and out1 pins can be utilized as synchronous switches between active low and tri-state.
fractional-n rf/integer-n if dual pll s1m8836/37 6 equivalent circuit diagram clock, data, le fold oscin cp o rf, cp o if f in rf, f in rf, f in if, f in if f in rf, f in if f in rf, f in if v bias
fractional-n rf/integer-n if dual pll s1m8836/37 7 absolute maximum ratings characteristics symbol value unit power supply voltage v dd 0.0 to 4.0 v voltage on any pin with gnd = 0 volts v i -0.3 to v dd + 0.3 v power dissipation p d 600 mw operating temperature t a -40 to +85 c storage temperature t stg -65 to +150 c electrostatic characteristics characteristics pin no. esd level unit human body model all < 2000 v machine model all < 300 v charge device model all < 800 v note: these devices are esd sensitive. these devices must be handled in an esd protected environment.
s1m8836/37 fractional-n rf/integer-n if dual pll 8 electrical characteristics (v dd =3.0v, v p =3.0v, t a = 25 c, unless otherwise specified.) characteristic symbol test conditions min. typ. max. unit power supply voltage v dd 2.7 3.0 4.0 v v p v dd 3.0 4.0 power supply s1m8836 rf+if i dd fractional-n mode 5.5 ma current s1m8837 rf+if (f osc =19.68mhz, rf r=2) 7.5 s1m8836 rf+if quiescent state 4.0 s1m8837 rf+if 6.0 if only 1.5 power down current i pwdn v dd =3.0v 1 10 m a digital inputs: clock, data and le high level input voltage v ih v dd =2.7v to 4.0v 0.7v d d v low level input voltage v il v dd =2.7v to 4.0v 0.3v d d v high level input current i ih v ih =v dd =4.0v -1.0 +1.0 m a low level input current i il v il =0v, v dd =4.0v -1.0 +1.0 m a reference oscillator input: osc in input current i ihr v ih =v dd =4.0v +100 m a i ilr v il =0v, v dd =4.0v -100 m a digital output: fold high level output voltage v oh i out =-500 m a v dd -0.4 v low level output voltage v ol i out =+500 m a 0.4 v
fractional-n rf/integer-n if dual pll s1m8836/37 9 electrical characteristics ( continued) (v dd =3.0v, v p =3.0v, t a = 25 c, unless otherwise specified.) characteristic symbol test conditions min. typ. max. unit charge pump outputs: cp o rf, cp o if rf charge pump output current i cprf source_min v cp =v p /2, rf_cp_word=0000 -50 m a i cprf- sink_min v cp =v p /2, rf_cp_word=0000 +50 m a i cprf- source_max v cp =v p /2, rf_cp_word=1111 -800 m a i cprf- sink_max v cp =v p /2, rf_cp_word=1111 +800 m a if charge pump output current i cprf source_min v cp =v p /2,cp_gain_8=0 -100 m a i cprf sink_min v cp =v p /2,cp_gain_8=0 +100 m a i cprf source_max v cp =v p /2,cp_gain_8=1 -800 m a i cprf sink_max v cp =v p /2,cp_gain_8=1 +800 m a charge pump leakage current i cpl 0.5v v cp vp-0.5v -2.5 +2.5 na sink vs. source mismatch i cp-sink vs i cp-source v cp =v p /2 3 10 % output current magnitude variations. voltage i cp vs v cp 0.5v v cp v p -0.5v 10 15 % output current vs. temperature i cp vs t a v cp =v p /2 10 % operating frequency, input sensitivity (programmable divider, pfd) rf operating frequency s1m8837 f in rf fractional-n mode (f osc =19.68mhz, rf r=2) 0.5 2.5 ghz s1m8836 fractional-n mode (f osc =19.68mhz, rf r=2) 0.25 1.0 ghz if operating frequency f in if v dd =3.0v 45 520 mhz reference oscillator input frequency osc in 2 40 mhz phase detector operating frequency f pd 10 mhz rf input sensitivity p fin rf v dd =3.0v -15 0 dbm v dd =4.0v -10 0 dbm if input sensitivity p fin if v dd =2.7v to 4.0v -10 0 dbm reference oscillator input sensitivity v oscin 0.5 v dd v pp
s1m8836/37 fractional-n rf/integer-n if dual pll 10 electrical characteristics ( continued) (v dd =3.0v, v p =3.0v, t a = 25 c, unless otherwise specified.) characteristic symbol test conditions min. typ. max. unit serial data control clock frequency f clock 10 mhz clock pulse width high t cwh 50 ns clock pulse width low t cwl 50 ns data set up time to clock rising edge t ds 50 ns data hold time after clock rising edge t dh 10 ns le pulse width t lew 50 ns clock rising edge to le rising edge t cle 50 ns
fractional-n rf/integer-n if dual pll s1m8836/37 11 functional description f o ld data out multiplexer clock data le cp o rf ? - d modulator rf n counter rf prescaler rf phase detector rf charge pump rf ld cmos output mux serial data control rf r counter osc in out0 f o ld cmos output mux out1 if charge pump cp o if if phase detector if ld if r counter if n counter if prescaler f in rf f in rf + - f in if f in if + - the samsung s1m8836/37 is rf/if dual frequency synthesizer ic which supports fractional-n mode for rf pll and integer-n mode for if pll depending on a program control. s1m8836/37 combined with an external lpf and an external vco forms pll frequency synthesizer. the frequency synthesizer consists of prescalers, pulse- swallowed programmable n counters, programmable reference r counters, phase detectors, programmable charge pumps, analog ld(lock detector), serial data control, etc. an input buffer in the prescaler amplifies the rf input power of -10dbm from the external rf/if vco to the sufficient ecl switching level to drive the following ecl divider so that it can be normally operated even in a smaller input power less than -10dbm. the amplified vco output signal is divided by the prescaler with a pre- determined divide ratio (div. 8/9/12/13 for s1m8836, div. 16/17/20/21 for s1m8837, div. 8/9 for if), the n counter and the fractional-n circuitry( s - d modulator). external reference signal is divided by the r counter to set the comparison frequency of the pfd. the divide ratios of the programmable counters can be programmed via the serial bus interface. these two signals drive the both inputs of the phase detector. the phase detector drives the charge pump by comparing frequencies and phases of the above two signals. the charge pump and the external lpf make the control voltage for the external vco and finally the vco generates the appropriate frequency signal.
s1m8836/37 fractional-n rf/integer-n if dual pll 12 when the pll is in the locked state, the rf vco's frequency will be n int + n frac times the comparison frequency, where n int is the integer divide ratio and n frac is the fractional component. the s1m8836/37 has new improved features compared to conventional integer-n plls. the fractional-n pll is available for the rf. the fractional synthesis frequency as is amps and is-95a/b/c. this makes it possible to widen the loop bandwidth as wide as 20khz or wider for a faster lock-up time and to improve the in-band phase noise performance due to the reduced divide ratio n. such s1m8836/37 in the fractional-n mode is suitable for cdma, gsm and pcs band applications. also, from the programmability of the charge pump, the users can easily design a stable loop by free selection of loop components and reach to the low spurious, the low power pll by an optimized current selection. prescaler the rf/if prescaler consists of a differential input buffer and ecl frequency dividers. the input buffer amplifies the input signal from the external vco to the required level set by sensitivity requirements. the output of the amplifier delivers a differential signal to the divider with the correct dc level. the buffer may be either single- ended or differentially driven. the single-ended operation is preferred in typical applications due to external vco. in this case, we recommend that the complementary input /fin of the input buffer be ac coupled to ground through external capacitors, even though it is internally coupled to ground via an internal 10pf capacitor. the other input pin fin of the buffer also needs external capacitor for decoupling the dc component and controlling the input power level. the rf prescalers of s1m8836 and s1m8837 provide 8/9/12/13 and 16/17/20/21 prescaler ratio, respectively. the if prescaler of s1m8836/37 contains 8/9 dual modulus prescaler. reference oscillator inputs the reference oscillator frequency is provided by an external reference such as tcxo through the osc in . it drives both the if r and rf r counters. programmable dividers (rf/if n counters) the rf n counter can be configured as a fractional counter. the fractional-n counter is selected when the frac-n_sel bit becomes high. in the fractional mode, the s1m8836 is capable of offering a continuous integer divide range from 25 to 1023 and the s1m8837 offering a continuous integer divide range from 49 to 2047. the s1m8836/37 if n counter supports an integer counter mode only, not including fractional counter, and is capable of operating from 45mhz to 520mhz offering a continuous integer divide range from 72 to 32767.
fractional-n rf/integer-n if dual pll s1m8836/37 13 s s - d d modulator the rf part of s1m8836/37 adopts the s - d modulator as a core of the fractional counter that makes it possible to obtain divide ratio n to be a fractional number between two contiguous integers. the s - d modulator effectively randomizes the quantization noise generated from digitizing process and results in extreme suppression of in-band noise power by pushing it out to out-of-band as in conventional s - d data converter. this technique eliminates the need for compensation current injection into the loop filter and improves fractional spurious performance, suitable for high-tier applications. the s - d modulator operates only for fractional-n mode, when the frac-n_sel is high. for proper use of the fractional mode, the user should be kept in mind that 1. a fractional number should be set in the range from -0.5 to 0.5 in step of 1/62976. 2. for s1m8836/7, r can be selected 1-3. the clock frequency fixed at 9.84mhz (=19.68mhz/2, r=2) is recommended for the s - d modulator which is an optimum condition for achieving good electrical performances related to the fractional noise and power consumption. only when using this clock frequency, the s1m8836/37 guarantees the exact frequency resolutions: 10khz for cdma pcs and 30khz for cdma cellular. note that the clock frequency much lower than 9.84mhz can deteriorate the fractional noise performance. users can use r=1 or r=3, too. for the case of r=1 or r=3, users must ask samsung for details. fractional noise performance may become better for r=1 (clock frequency=19.68mhz/1=19.68mhz). but the rf operating frequency range may be shrinked for that case of r=1. phase-frequency detector (pfd) and charge pump (cp) the rf/if phase detector composed of pfd and cp outputs pump current into an external loop filter in proportional to the phase difference between outputs of n and r counter. the phase detector has a better linear transfer characteristic due to a feedback loop to eliminate dead zone. the polarity of the pfd can be programmed using rf_pfd_pol/if_pfd_pol depending on whether rf/if vco characteristics are positive or negative. (programmable descriptions for phase detection polarity) power-down(or power-save) control each pll is individually power controlled by the enable pins (rf_en and if_en pins) or program control bits (pwdn, pwdn_rf/if). the enable pins override the program control bits. when both enable pins are high, the program control bits determine the state of power control. power down forces all the internal blocks to be deactivated and the charge pump output to be in the tristate. the control register, however, remains active for serial programming and is capable of loading and latching in data during the power down.
s1m8836/37 fractional-n rf/integer-n if dual pll 14 programming description the s1m8836/37 can be programmed via the serial bus interface. the interface is made of 3 functional signals: clock, data, and latch enable(le). serial data is moved into the 22-bit shift register on the rising edge of the clock. these data enters msb first. when le goes high, data in the shift register is moved into one of the 4 latches (by the 2-bit control). data[21:2] ctl[1:0] lsb msb data flow (msb first) control bit map (ctl[1:0]) control bits data location ctl2(ctl[1]) ctl1(ctl[0]) 0 0 word1 0 1 word2 1 0 word3 1 1 word4 data bit map (data[21:2]) first bit register bit location last bit 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 word1(w1) if_ctl_ word rf_r (2bit) if _r_cntr(15bit) 0 0 word2(w2) cmos if_cp_ word if_nb_cntr(12bit) if_na_ cntr(3bit) 0 1 word3(w3) fold(4bit) rf_cp_word rf_nb_cntr(7bit) rf_na_cntr (36:3bit) rf_na_cntr (37:4bit) 1 0 word4(w4) rf_ctl_ word frac_cntr(17bit) 1 1
fractional-n rf/integer-n if dual pll s1m8836/37 15 data bit map (data[21:2]) (continued) control words control bits acronym low (0) high (1) comments if_ctl_word w1[21] if_cnt_rst normal operation if counter reset if w1[20] pwdn_if power up power down if w1[19] pwdn asynchronous power down synchronous power down rf and if cmos w2[21] speedy_lock cmos output speedy_lock mode w2[20] out1 voltage low voltage high pin #23 w2[19] out0 voltage low voltage high pin #24 if_cp_word w2[18] if_cp_gain 1x 8x if charge pump w2[17] if_pfd_pol negative slope positive slope if pfd fold w3[21:18] fold select lds and monitoring mode of internal counters. ( fold control for control codes in detail) lock detector(ld), test mode rf_cp_word w3[17:14] rf_cp_lvl select 16-level charge pump current (rf charge pump gain for control codes in detail) rf charge pump w3[13] rf_pfd_pol negative slope positive slope rf pfd rf_ctl_word w4[21] rf_cnt_rst normal operation rf counter reset rf w4[20] pwdn_rf power up power down rf w4[19] frac-n_sel integer-n mode fractional-n mode rf; pll mode selection ? counter reset mode resets r & n co unters. ? if charge pump current can be selected to high current(8x) or low current(1x) mode. ? in the speedy_lock mode, the out0 and out1 pins can be utilized as synchronous switches between active low and tri-state. the speedy_lock mode activates the out0 and out1 pins to be connected to ground with a low impedance(< 150 w ) while a high charge pump gain( 3 8x) is selected and otherwise to the tristate. ? for using a programmable cmos output, the cmos output bit(w2[21]=l) should be activated and then th e desired logic level should be programmed with the control bits w2[19] for out0 and w2[20] for out1.
s1m8836/37 fractional-n rf/integer-n if dual pll 16 programmable reference counter(w1[18:2]) if the control bit is 00, data is moved from the 22-bit shift register into the r-latch which sets the if reference counter. serial data format is shown in the table below. msb w1[21:0] lsb if_ctl_word[21:19] rf_r_cntr[[18:17]: 1~3 if_r_cntr[16:2]: 3~32767 0 0 21 19 18 17 16 2 1 0 program code division ratio of the rf r counter,rf_r_cntr division ratio of the if r counter, if_r_cntr control bits 15-bit if r counter division ratio division ratio : 3 to 32767(the divide ratios less than 3 are prohibited) data are shifted in msb first. division ratio 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 32767 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 rf r counter division ratio division ratio : 1 to 3 division ratio 1 0 1 0 0 1 0 1 2 1 0 3 1 1
fractional-n rf/integer-n if dual pll s1m8836/37 17 programmable counter(n counter) if the control bits are 01(if), 10, and 11(rf), data is transferred from the 22-bit shift register into the n/ frac- latch. n counter consists of swallow counter(a counter; 3-bit for if & s1m8836rf and 4-bit for s1m8837rf), main counter(b counter; 7-bit for s1m8836/37 rf and 12-bit for if), and fractional counter(f counter; 17-bit for s1m8836/37 rf). serial data format is shown below. if n counter msb w2[21:0] lsb cmos if_cp_word [18:17] if_nb_cntr[16:5] : 3 - 4095 21 17 16 2 1 0 program code division ratio of the if n counter control bits if_na_cntr[4:2] : 0 - 7 0 1 19 18 5 4 if main counter division ratio(b counter ) if_nb_ cntr[16:5] ; for s1m8836/37 division ratio(b) 11 10 9 8 7 6 5 4 3 2 1 0 3 0 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 0 1 0 0 4095 1 1 1 1 1 1 1 1 1 1 1 1 division ratio: 3 to 4095 (the division ratios less than 3 are prohibited) swallow counter division ratio (a counter) if_na_cntr[4:2] ; for s1m8836/37 division ratio(a) 2 1 0 0 0 0 0 1 0 0 1 7 1 1 1 division ratio: 0 to 7, b>a
s1m8836/37 fractional-n rf/integer-n if dual pll 18 rf n counter msb w3[21:0] lsb f o ld[21:18] rf_cp_word [17:13] rf_nb_cntr[12:6] : 3 ~ 127 21 13 12 2 1 0 program code division ratio of the rf n counter control bits rf_na_cntr[5:2] 1 0 18 17 6 5 rf main counter division ratio (b counter) rf_nb_ cntr[12:6] ; for s1m8836/37 division ratio(b) 6 5 4 3 2 1 0 3 0 0 0 0 0 1 1 4 0 0 0 0 1 0 0 7 1 1 1 1 1 1 1 division ratio : 3 to 127 (the division ratios less than 3 are prohibited) rf swallow counter division ratio (a counter) rf_na_cntr[5:2] ; for s1m8836 division ratio(a) 3 2 1 0 0 x 0 0 0 1 x 0 0 1 7 x 1 1 1 division ratio : 0 to 7 x = don't care condition rf_na_cntr[5:2] ; for s1m8837 division ratio(a) 3 2 1 0 0 0 0 0 0 1 0 0 0 1 15 1 1 1 1 note: division ratio: 0 to 15 x = don't care condition
fractional-n rf/integer-n if dual pll s1m8836/37 19 rf fractional counter msb w4[21:0] lsb rf_ctl_word[21:19] frac_cntr[18:2] 21 19 18 2 1 0 program code division ratio of the rf fractional counter control bits 1 1 rf fractional counter value (f counter) frac_ cntr[18:2] ; for s1m8836/37 rf counter value (f) f 16 f 15 f 14 f 13 f 12 f 11 f 10 f 9 f 8 f 7 f 6 f 5 f 4 f 3 f 2 f 1 f 0 31488 0 0 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 -31488 1 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 f counter value: -31488(2's complementary) to 31488 note: for a negative integer, the counter value should be inputted as the corresponding 2's complementary binary code. for instance, the 2's complementary binary code of -2 is 1 1111 1111 1111 1110.
s1m8836/37 fractional-n rf/integer-n if dual pll 20 programmable pfd and charge pump if charge pump gain ( if_cp_word; w2[18] ) control words control bits acronym low (0) high (1) comments if_cp_word w2[18] if_cp_gain 1x (100 m a) 8x (800 m a) if charge pump rf charge pump gain ( rf_cp_word; w3[17:14] ) control words control bits acronym low (0) high (1) comments rf_cp_word w3[17:14] rf_cp_lvl select 16-level charge pump current rf charge pump icpo ( m m a) 8x 4x 2x 1x w3[17] w3[16] w3[15] w3[14] 50 0 0 0 0 100 0 0 0 1 200 0 0 1 1 250 0 1 0 0 400 0 1 1 1 450 1 0 0 0 800 1 1 1 1 phase detector polarity ( rf_cp_word/if_cp_word; w3[13]/w2[17] ) depending on vco characteristics, w2[17] and w3[13] bits should be set as follows : control bits low (0) high (1) comments w2[17] negative slope positive slope if pfd w3[13] negative slope positive slope rf pfd
fractional-n rf/integer-n if dual pll s1m8836/37 21 (1) vco characteristics vco output frequency vco input voltage (2) program mode control power down mode operation control words control bits acronym low (0) high (1) comments if_ctl_word w1[20] pwdn_if power up power down if w1[19] pwdn asynchronous power down synchronous power down rf and if rf_ctl_word w4[20] pwdn_rf power up power down rf each pll is individually power controlled by the enable pins (rf_en and if_en pins) or program control bits (pwdn, pwdn_rf/if). the enable pins override the program control bits. when both enable pins are high, the program control bits determine the state of power control. power down forces all the internal analog blocks to be deactivated and the charge pump output to be in a tristate. the oscillator buffer is powered down when the power down bits (w4[20] and w1[20]) become high. the control register and r/n counters, however, remains active for permitting serial programming and is capable of loading and latching in data during the power down. there are synchronous and asynchronous power-down modes for s1m8836/37. the power-down bit w1[19] is used to select between synchronous and asynchronous power-down. synchronous power-down mode occurs if w1[19] bit is high and then the power down bit (w4[20] or w1[20]) becomes high. in the synchronous power down mode, the power-down function will go into power-down mode upon the completion of a charge pump pulse event because it is synchronized with the charge pump and thus can diminish undesired frequency jumps. asynchronous power down mode occurs if w1[19] bit is low and then the power down bit (w4[20] or w1[20]) becomes high. activation of the asynchronous function will go into power-down mode immediately. rf power down mode table w4[20] w1[19] power down mode status 0 0 rf pll active 0 1 rf pll active, only charge pump to tristate 1 1 asynchronous power down 1 1 synchronous power down
s1m8836/37 fractional-n rf/integer-n if dual pll 22 if power down mode table w1[20] w1[19] power down mode status 0 0 if pll active 0 1 if pll active, only charge pump to tristate 1 0 asynchronous power down 1 1 synchronous power down programmable counter reset control control words control bits acronym low (0) high (1) comments if_ctl_word w1[21] if_cnt_rst normal operation if counter reset if rf_ctl_word w4[21] rf_cnt_rst normal operation rf counter reset rf counter reset mode resets r & n counters. rf fractional-n selection control words control bits acronym low (0) high (1) comments rf_ctl_word w4[19] frac_n_sel reserved fractional-n mode rf;pll mode selection cmos output control control words control bits acronym low (0) high (1) comments cmos w2[21] speedy lock cmos output speedy lock mode w2[20] out1 voltage low voltage high pin #23 w2[19] out0 voltage low voltage high pin #24 in the speedy lock mode, the out0 and out1 pins can be utilized as synchronous switches between active low and a tri-state. the speedy lock mode activates the out0 and out1 pins to be connected to ground with a low impedance(< 150 w ) while a high charge pump gain( 3 8x) is selected and otherwise to a tri-state. for using a programmable cmos output, the cmos output bit(w2[21]= low) should be activated and then the desired logic level should be programmed with the control bits w2[19] for out0 and w2[20] for out1.
fractional-n rf/integer-n if dual pll s1m8836/37 23 fold control control words control bits acronym low (0) high (1) comments fold w3[21:18] fold select lds monitoring mode of internal counters. lock detector (ld), test mode fold[3] fold[2] fold[1] fold[0] fold output state 0 0 0 0 disabled(default low) 0 0 0 1 rf and if analog lock detect 0 0 1 0 reserved test mode 0 0 1 1 reserved test mode x 1 0 0 reserved test mode x 1 0 1 if r counter output x 1 1 0 if n counter output x 1 1 1 rf r counter output 1 0 0 0 rf n counter output 1 0 0 1 reserved test mode 1 0 1 0 reserved test mode 1 0 1 1 reserved test mode ? when the pll is locked and the analog lock detect mode is selected, the fold output is high, with narrow pulses low. lock detector(ld) there is analog mode for s1m8836/37. the fold bits, w3[21:18], are used to select the lock detection mode and to output the selected lock signal through the fold pin. the fold output becomes high with narrow pulsed low while both rf and if plls are locked and thereby the output should be low-pass filtered for a dc locked voltage high.
s1m8836/37 fractional-n rf/integer-n if dual pll 24 pulse swallow function the rf vco frequency f voc becomes n int + n frac times the comparison frequency(f osc /r) where n int is the integer divide ratio and n frac is the fractional component; f vco = (n int + n frac ) f osc /r = n f osc /r where n int = p b + a rf pll: n frac = f/62976, -31488 f 31488, and r = 1, 2, 3 (typically 2) if pll: n frac = 0, b > a and 3 r 32767 f vco : external vco output frequency f osc : external reference frequency(from external oscillator) r: preset divide ratio of programmable r counter (rf: 1, 2, 3(typically 2), if: 3 to 32767); p: preset modulus of quadruple modulus prescaler (s1m8836 rf:p=8, s1m8837 rf:p=16, if:p=8) b: preset value of main counter (s1m8836/37 rf: 3 to 127, if: 3 to 4095) a: preset value of swallow counter division ratio (s1m8836 rf: 0 a 7, s1m8837 rf: 0 a 15. if: 0 a 7, a fractional-n rf/integer-n if dual pll s1m8836/37 25 serial data input timing data clock le data[21] msb lsb ctl[0] ctl[1] data[20] data[10] data[9] le t ds t d h t cwh t d h t l ew t c le or phase detector and charge pump characteristics phase difference detection range : -2 p to +2 p when the positive-slope polarity of pfd is selected, w2[17]=high or w3[13]=high; f r ld cp o f p fr > fp fr = fp fr < fp fr < fp fr < fp
s1m8836/37 fractional-n rf/integer-n if dual pll 26 simplified schematic diagram for rf sensitivity test rf signal generator 10db attn frequency counter pc parallel port 50 w microstrip 100pf f in f in osc in fold 51 w 100pf 100pf 100pf 2.2 m f 2.2 m f le data clock v p v dd 2.7v - 4.0v 12k w 39k w s1m8836/37 ? sensitivity limit is determined when the error of the divided rf output ( fold) becomes 10hz. ? f vco = 1.0ghz, n = 100 , p = 8, r = 2 in s1m8836 integer-n test mode f vco = 2.1ghz, n = 210 , p = 16, r = 2 in s1m8837 integer-n test mode typical application example
fractional-n rf/integer-n if dual pll s1m8836/37 27 typical application circuit 9 8 osc in v dd rfa 7 6 gnd rf f in rf 5 4 f in rf dgnd 3 2 cp o rf v p rf v dd rf 13 14 15 16 17 18 19 20 21 clcok data le gnd if f in if f in if dgnd cp o if v p if 10 11 12 fold rf_en if_en 24 23 22 out0 out1 v dd if vco vco reference input 1000pf 51 w 100pf 10pf rf out 10pf r in c3 c2 r3 r1 c1 100pf 0.01 m f v p 0.1 m f 22 w v dd v p 100pf 0.01 m f 100pf 0.01 m f r11 c11 c12 c13 r13 r in 56pf 56pf if out 1000pf from controller v dd fold 1 v dd 22 w 0.1 m f 100pf 0.01 m f v dd 22 w 0.1 m f 100pf 0.01 m f . cdma : ucva4x103a . k-pcs : ucvw4x102a . us-pcs : ucva3x120a ? the role of rin : rin makes a large portion of vco output power go to the load rather than the pll. the value of rin depends on the vco power level
fractional-n rf/integer-n if dual pll s1m8836/37 28 pcb layout guide in doing pcb layouts for s1m8836/37, we recommend that you apply the following design guide to your handsets, thus improving the phase noise and reference spurious performances of the phones. 1. the s1m8836/37 has external four power supply pins to sup ply on-chip bias, each for analog and digital blocks of rf and if plls. basically in doing pcb layout, it is important that power supply lines should be separated from one another and thus coupling noises through the voltage supply lines can be minimized. if you have some troubles with the direction to separate, you can choose the following recommendations for your convenience; tying analog power lines, v dd rf and v dd if, is possible. tying digital power lines, v p1 and v p2 , is possible. a point connecting the analog and digital power lines should be near to battery line as close as possible. it minimizes coupling noise effects from a digital switching noise into analog blocks. we also recommend that a passive rc low pass filter(r(22 w ),c(100nf)) be utilized for suppressing high frequency noise on the analog power supply line and reducing any digital noise couplings. 2. vco power lines should be well separated from those of pll because vco is generally a very sensitive device from power line noises and pll is a digital noise generator. 3. for more improvement of reference spurious performance, it is recommended that the lpf ground be tied to the pll ground, not the vco ground.
fractional-n rf/integer-n if dual pll s1m8836/37 29 package dimensions 0.27 + 0.05 0.70 + 0.05 1.00max 3.50 + 0.10 4.50 + 0.10 b a #1 index area c 0.08 c (0.05) 0.10 2x4.00 0.10 c 2x (0.05) #24 4x0.50 + 0.10 #1 #1 id mark 0.10 c 2x 20x0.50 2x1.00 24x0.30 + 0.05 m c b c s

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